In memory systems, including those utilizing dynamic random access memory (DRAM) arrays, it is known to use a static register to store a part or the whole of the contents of a word line of the memory array. This enables the data bits in the static register to be selectively coupled via an output buffer for further processing after the data bits have been read out of the memory.
Referring now to FIG. 1, there is shown a prior art memory system 2 comprising a memory array and control circuitry 26 (shown within a dashed rectangle), a RE Phases Generator 10, a CE phases Generator 12, a static register and data 1/0 control 14, address buffers 16, address transition detector 18, address latches and register predecoders 20, static register and decoder 22, and a data I/O and multiplexer 24. Memory array and control circuitry 26 comprises row address latches and predecoder control 28, column address latches and predecoder control 30, row decoder 32, column decoder 36 and memory array and sense amplifiers 34.
In the operation of the system 2 of FIG. 1, the data bits contained in the static register 22 must be transferred out of the register before the next row (not shown) of the memory array 34 to-be-read can be precharged. This presents a problem since for continued read-out of the static register 22, a signal [RAS or RE] enabling the memory array 34 must remain in the enabling condition until the last location is read out of the static register 22. This means that the cycle time to read each row must include the time to actually read out the contents of a row (TR) as well as the time to precharge that row (TP).
In the operation of the system 2 of FIG. 1, a user generated read enable (RE) signal also referred to herein as RAS is coupled to a terminal 301 which is connected to an input (denoted by the letter "a") of RE phases generator 10. RE phases generator 10 functions to detect a read enable (RE) signal condition. For purpose of illustration herein, the read enable (RE) condition occurs when an RE or Row Address Strobe (RAS) signal goes from a high level or logic "1" to a low level or logic "0". Also, in the discussion to follow, the terms RE and RAS are used interchangeably.
In response to a RE enable condition, generator 10 then generates two output signals, FAST RASIN (FRASIN) at an output b and RASIN at an output c for use within the memory system. The FRASIN signal at output "b" is coupled to the address buffers 16, CE Phases generator 12 and static register and data I/O control 14. The RASIN signal at output "c" is coupled to the row and column address latch predecoders control 28 and 30 and to the static register and data I/O control 14.
The structure and function performed by Generator 10 may be better understood by reference to the more detailed showing of FIG. 2.
Referring now to FIG. 2, there is shown a prior art embodiment of the generator 10 of FIG. 1 which comprises a RASIN BUFFER 303 and a FAST RASIN buffer 305. A user generated read enable (RE or RAS) signal is applied to an input terminal 301 and is shown in waveform "a" of FIG. 3. The FAST RASIN BUFFER 305 has an input (IN) connected to node "a" which is connected to terminal 301 and an output "b" at which is produced an output signal denoted as FAST RASIN or FRASIN and shown in waveform "b" of FIG. 3. RASIN BUFFER 303 has an input (IN1) connected to node "a" and another input, IN2, which is coupled to the output "b" of FAST RASIN BUFFER 305. The RASIN BUFFER 303 has an output "c" at which is produced an output signal denoted as RASIN and shown in waveform "c" of FIG. 3. The FRASIN signal is coupled via line 11b to the CE Phases Generator 12, to address buffers 16 and to static register and data I/O control 14 as shown in FIG. 1. The RASIN signal is coupled via line 11a to row and column address latches and predecoder control 28 and 30 and to the static register and data I/O control 14 as is shown in FIG. 1.
Referring now to FIG. 3, note that the RAS signal goes low at time t0. In response thereto and a short time delay thereafter, the FRASIN signal goes low at time t1. Then, in response to RAS being low and FRASIN going low, the RASIN signal goes low at time t2, a short time delay after FRASIN goes low. However, note that after RAS goes high at time t3, both FRASIN and RASIN terminate (i.e., go high or logic "1") at the same time(i.e., t4). The reason for delaying RASIN going low relative to FRASIN going low is to ensure that the FRASIN signal enables the outputs of address buffers 16 and causes them to be valid prior to RASIN enabling the selection of the appropriate row of the memory array 34.
For a better understanding of the explanation to follow, a brief description of parts of the memory system 2 of FIG. 1 is set forth below.
(A) CE phases generator 12 detects changes in a column enable (CE) or column address strobe (CAS) signal and produces a CASIN signal for internal use. The CRASIN signal functions to activate the bit decode circuitry (i.e. blocks 30 and 20) associated with the array 26 and the static register 22 and provides an enabling control signal to the static register and data I/O control 14.
(B) Static Register and Data I/O Control 14 functions to provide read and write commands to or from the static register 22 and the DATA I/O 24.
(C) Address Buffers 16, which has inputs A0 through A11, generates internal address information used for both row and column selection. The FRASIN output of generator 10 is coupled to BUFFERS 16 which are turned on and off by the FRASIN signal.
(D) Address Transition Detector 18 produces new read or write accesses (enabling signals) from or to the static register control 14 which then supplies control signals to static register 22 and DATA I/O 24 when an address transition (or change) is detected for a static column mode component. Any address change during a read cycle initiates a valid read access (enable) which is completed if no further address changes are detected.
(E) Address Latches Register Predecoders 20--The address latches only operate for PAGE mode components and simply pass address buffer information to the predecoders for static column mode operation. PAGE mode operation captures address information when CAS (or CE) become active (low).
(F) Static Register and Decoder 22--Contains data line information read out from the array 34 for every read enable and column enable signal. Every read from the memory comes through the static register 22 which is loaded from the memory array once with every RE and CE access. When the RE signal returns to the precharge or standby condition, the contents of the static register are written back into the memory array. During write cycles, data bits are changed within the static register which then update the memory array when RE goes from the enable (low) to the disable (high) condition. The decoder 22 decodes the remaining column enable (CE) address decodes which were not used in the array and determine which register bit is to be written or read.
(G) Data I/O and Multiplexer 24--Is a block of logic which controls which of two data bits is to be read or written. Also, a latch (in block 24) holds the last bit read from the register 22 until the next valid read cycle. The static register and data I/O control 14 determines whether the Data I/O 24 and register 22 receives data from or supplies data to the memory system.
(H) Memory array 26 includes a matrix array 34 of dynamic random access memory (DRAM) cells and sense amplifiers which store information for future use. Array 26 also includes row address latches predecoder control 28 which is enabled by RASIN and with row decoder 32 controls which row of array 34 is selected for read-out. Array 26 also includes column address latches predecoder control 30 which is enabled by RASIN and CASIN signals and which produces outputs applied to column decoder 36 which function to decode the bit lines and thus selects which bit lines gets coupled to the data lines and fed into (or out of) the Static Register 22.
In the operation of the memory system 2 of FIGS. 1 and 2, the read cycle of a DRAM is initiated by the application of a RAS [ROW ENABLE--RE-] signal which goes from a precharge or standby condition (e.g., high or logic "1") to an enable condition (e.g., low or logic "0"). The RAS signal is used to generate a FRASIN signal which is applied to, and enables, the CE phases generator 12, static generator control 14 and address buffers 16. The RAS signal is also used to generate a RASIN signal which enables the contents of a word line of the memory array to be read out onto the bit lines (columns). The data on the bit lines are amplified by sense amplifiers coupled to the bit lines for generation of better defined signals which are either close to ground potential or to the voltage level of a power supply (e.g., Vdd) used with the memory array and sense amplifiers 34. The information on selected bit lines are then decoded onto data lines which are coupled to static register 22 from which the data bits can be selectively read out via DATA I/O 24 to other utilization circuits. However, when the RAS signal goes from the enable condition to the precharge condition, CE phases generator 12, static register control 14 and address buffers 16 are disabled and the data stored in static register 22 can no longer be read-out. Thus, in the memory system 2 of FIG. 1, the RAS signal must be maintained in its enable condition and a new row of the memory array can not be precharged so long as the contents of static register 22 have to be read-out. This effectively increases read cycle time and thus the total cycle time of the memory system 2.
It is desirable to have a memory system which has improved read cycle time as compared to memory system 2.